Recruiter Name:Angelo Escalante, John Tayag, Karl Carada, Leslie Faustino, Melody Papa, Stephany Joy Pastrana
OorwinOOJ - 9183
Principal FPGA Verification Engineer
Location: Pasadena, CA
Pay range: $70-$95/hour
As a Principal FPGA Verification Engineer, you will lead the planning and execution of highly sophisticated and unique electronics systems with Laboratory wide impact. Specific responsibilities include:
Verify that FPGA/ASIC designs are flight worthy
Improve FPGA verification flow
Improve verifying hardware resilience
Mentor junior engineers
Expert in architecting, designing, and implementing Block and System-level UVM/UVMF constrained random verification environments.
Expert coding in System Verilog
Expert creating a verification plan and functional coverage matrix from requirements and design specification.
Demonstrated experience leading a verification team and presenting in design reviews
Must have experience through an FPGA/ASIC full life cycle from initial concept to burn review/tapeout.
Success infusing new verification technologies and methodologies
Skillfully handles fast pace and dynamic product development environment
Excellent written/verbal communication skills
Bachelor’s degree in Electronics, Electrical, or Computer Engineering or related discipline with typically a minimum of 12 years of related experience; Master’s in similar disciplines with a minimum of 10 years of related experience; or PhD in similar disciplines with a minimum of 8 years of related experience
Experience with Mentor Questa Verification tool suite and Questa Verification IP
Experience in bus standards protocol such as: SpaceWire, PCI, MILSTD-1553, CAN, and Ethernet
Experience integrating Matlab/Simulink models into a UVM verification environment
Experience with SVA and static formal model checking